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PRELIMINARY DATA SHEET
SDA 9401 SCARABAEUS
Scan Rate Converter using Embedded DRAM Technology Units
Edition Feb. 28, 2001 6251-558-1PD
Document Change Note
DS1 Date Section/ Page Changes compared to previous issue Department
25.09.98 05.05.99 01.07.99 page 61 page 20
Changes to previous issue Version 0, Edition 05/98 HL IV CE are marked with a changebar ESD model CDM added, -1.5 kV, ..., 1,5 kV IV CE
In Multipicture mode only STOPMODE = 0110 pos- IV CE sible Preliminary Data Sheet Version 01, Edition 04/00 CNP HN PD update new logo, removal of change bars
26.04.00
all
1)... DS = Document state, compares to block 4 of document number
Micronas
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Preliminary Data Sheet
SDA 9401 List of Tables 1 2 3 4 5 Page General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Input sync controller (ISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Input format conversion (IFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 Low data rate processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 Vertical compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Horizontal compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Multipicture display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.4 6.5
6.5.1 6.5.2 6.5.3 6.5.4
Clock concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output sync controller (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
HOUT generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 VOUT generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Operation mode generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Window generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.6 6.7 6.8
6.8.1 6.8.2 6.8.3 6.8.4
Output format conversion (OFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 High data rate processing (HDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IC bus slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 IC bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 IC bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7 8 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . . . . 64 66 66 66 67 67
10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 IC-bus timing START/STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 IC-bus timing DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Timing diagram clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Clock circuitry diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Micronas 3 Preliminary Data Sheet
SDA 9401
1
General description
The SDA 9401 is a new component of the Micronas MEGAVISION(R) IC set in a 0.35 m embedded DRAM technology (field memory embedded). The SDA 9401 is pin compatible to the SDA 9400 (frame memory embedded). The SDA 9401 comprises all main functionalities of a digital featurebox in one monolithic IC. The SDA 9401 does a simple 100/120 Hz interlaced (50/60 Hz progressive) scan rate conversion. The scan rate converted picture can be vertically expanded. The SDA 9401 has a freerunning mode, therefore features like multiple picture display (e.g. tuner scan) are possible. The noise reduction is field based. Furthermore separate motion detectors for luminance and chrominance have been implemented. For automatic controlling of the noise reduction parameters a noise measurement algorithm is included, which measures the noise level in the picture or in the blanking period. In addition a spatial noise reduction is implemented, which reduces the noise even in the case of motion. The input signal can be compressed horizontally and vertically with a certain number of factors. Therefore split screen modes are supported too. Beside these additional functions like coloured background, windowing and flashing are implemented.
2 * * * * *
Features
Two input data formats - 4:2:2 luminance and chrominance parallel (2 x 8 wires) - ITU-R 656 data format (8 wires) Two different representations of input chrominance data - 2`s complement code - Positive dual code Flexible input sync controller Flexible compression of the input signal - Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0) - Digital horizontal compression of the input signal (1.0, 2.0, 4.0) Noise reduction - Motion adaptive spatial and temporal noise reduction (3D-NR) - Temporal noise reduction for luminance field based - Temporal noise reduction for chrominance field based - Separate motion detectors for luminance and chrominance - Flexible programming of the temporal noise reduction parameters - Automatic measurement of the noise level (5 bit value, readable by IC bus) TV mode detection by counting line numbers (PAL, NTSC, readable by IC bus) Embedded memory - 3.2 Mbit embedded DRAM core for field memories - 128 kbit embedded DRAM core for line memories 4 Preliminary Data Sheet
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Micronas
SDA 9401
* * * * *
Flexible clock and synchronization concept - Decoupling of the input and output clock system possible Scan rate conversion - Simple 100/120 Hz interlaced scan conversion (e.g. AABB, AA*B*B) - Simple progressive scan conversion (e.g. AA*) Flexible digital vertical expansion of the output signal (1.0, ... [1/32] ... , 2.0) Flexible output sync controller - Flexible positioning of the output signal - Flexible programming of the output sync raster Signal manipulations - Insertion of coloured background - Vertical and/or horizontal windowing with four different speed factors - Flash generation - Still field - Support of split screen applications - Multiple picture display - Tuner scan (4 and 16 times for 4:3, 12 times for 16:9 tubes) - Support of multi picture display with PIP or front-end processor with integrated scaler (e.g. 9 times display of PIP pictures, picture tracking, random pictures, still-in-moving picture, moving-in-still picture) IC-bus control (400 kHz) P-MQFP-64 package 3.3 V 5% supply voltage
* * *
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Preliminary Data Sheet
SDA 9401
3
Block diagram
HIN VIN SYNCEN
ISC Input sync controller
MC Memory Controller
OSC Output sync controller
VOUT HOUT HREF INTERLACED
ED eDRAM
YIN UVIN RESET
IFC Input format conversion
LDR Vertical, Horizontal decimation Noise reduction and measurement
Interfaces Data buffer Voltage control Test controller
HDR Scan rate conversion Vertical interpolation
OFC output format conversion
YOUT UVOUT CLKOUT bd9401s
IC IC Bus Interface
LM Line memory
PLL1 Clock doubling
LM Line memory
PLL2 Clock doubling
SDA
SCL
CLK1
X1/CLK2
X2
The SDA 9401 contains the blocks, which will be briefly described below: ISC - Flexible input sync controller IFC - Input format conversion LDR - Low data rate processing (noise reduction and measurement, vertical compression, horizontal compression) MC - Memory controller OSC - Flexible output sync controller OFC - Output format conversion HDR - High data rate processing (scan rate conversion, vertical expansion) IC - IC bus interface PLL1/2 - PLL for frequency doubling LM - Line memory core ED - eDRAM core
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Preliminary Data Sheet
SDA 9401
4
Pin configuration
YOUT5 VSS1 YOUT4 YOUT3 YOUT2 YOUT1 YOUT0 VSS1 VDD1 UVOUT7 UVOUT6 UVOUT5 UVOUT4 UVOUT3 UVOUT2 UVOUT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
YOUT6 YOUT7 HREF VOUT HOUT VDD2 VSS2 VDD2 VDD1 VSS1 CLK1 VDD2 VSS2 VDD2 YIN7 YIN6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SDA 9401
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 VSS1 VDD1 UVIN7 UVIN6 UVIN5 UVIN4 VSS2 VDD2 UVIN3 UVIN2 pin49401
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Micronas
UVOUT0 INTERLACED TEST SCL SDA VIN HIN VSS1 VDD1 CLKOUT X2 X1/CLK2 SYNCEN RESET UVIN0 UVIN1
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Preliminary Data Sheet
SDA 9401
5
Pin description
Pin No.
2,8,24,42,55 9,25,41,56 36,52,58 35,51,53,57, 59 43,..,50
Name
VSS1 VDD1 VSS2 VDD2 YIN0...7
Type
S S S S I/TTL I/TTL PD I/TTL
Description
Supply voltage ( VSS = 0 V ) Supply voltage ( VDD = 3.3 V ) Supply voltage ( VSS = 0 V ) Supply voltage ( VDD = 3.3 V ) Data input Y (see input data format) Data input UV (for 4:2:2 parallel, see input data format) (for CCIR 656, see input data format) System reset. The RESET input is low active. In order to ensure correct operation a "Power On Reset" must be performed. The RESET pulse must have a minimum duration of two clock periods of the system clock CLK1. H-Sync input (only for full CCIR 656) V-Sync input (only for full CCIR 656) Synchronization enable input I2C-Bus data line (5V ability) I2C-Bus clock line (5V ability) System clock 1 Data output UV (see output data format) Data output Y (see output data format) Horizontal active video output V-Sync output H-Sync output Interlace signal for AC coupled vertical deflection Crystal connection / System clock 2 Clock output (depends on IC parameters CLK11EN, CLK21EN, see also Clock concept on page 27) Test input, connect to VSS for normal operation
31,..,34;37,..., UVIN0...7 40 30 RESET
23 22 29 21 20 54 17,..,10 62 61 60 18 28 27 26 19
HIN VIN SYNCEN SDA SCL CLK1 UVOUT0...7 HREF VOUT HOUT X1 / CLK2 X2 CLKOUT TEST
I/TTL PD I/TTL PD I/TTL I/O I I/TTL O/TTL O/TTL O/TTL I/TTL I/TTL I/TTL O/TTL I/TTL
7,..,3;1;64;63 YOUT0...7
INTERLACED O/TTL
O/ANA Crystal connection
S: supply, ANA: analog Micronas
I: input,
O: output,
TTL: digital (TTL)
PD: pull down 8 Preliminary Data Sheet
SDA 9401
6
6.1
System description
Input sync controller (ISC)
Input signals
Signals Pin number Description
HIN
23
VIN
22
SYNCEN
29
horizontal synchronization signal (polarity programmable, IC bus parameter 01h HINPOL, default: high active) vertical synchronization signal (polarity programmable, IC bus parameter 01h VINPOL, default: high active) enable signal for HIN and VIN signal, low active (see also chapter Input format conversion (IFC) on page 12)
The input sync controller derives framing signals from the H- and V-Sync for the input data processing. The framing signals depend on different parameters and mark the active picture area. Input parameter
HIN pixels per line VIN lines per field
(VERPOS*2) (ALPFIP*2) (VERWIDTH*2) NALIP+PD
(HORPOS* (HORWIDTH*32)* 32)*CLK1 CLK1
PD - Processing Delay (NAPIPDL*4 + NAPIPPH + PD)* CLK1 (APPLIP*32)*CLK1
The distance between the incoming H-syncs in system clocks of clk1 must be even.
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inpar01
Preliminary Data Sheet
SDA 9401
Input write parameter
Parameter [Default value] Subaddress Description
NALIP [20] ALPFIP [144] NAPLIP NAPIPDL [0] NAPIPPH [0] APPLIP [45] PIMODE 1: on 0: off [0] VERPOS [0] VERWIDTH [0] HORPOS [0] HORWIDTH [0]
02h 03h 00h, 04h
Not Active Line InPut defines the number of lines from the V-Sync to the first active line of the field Active Lines Per Field InPut defines the number of active lines Not Active Pixels Per Line InPut defines the number of pixels from the H-Sync to the first active pixel of the line. The number of pixels is a combination of NAPIPDL and NAPIPPH. Active Pixels Per Line InPut defines the number of active pixels Picture Insert MODE allows the insertion of an arbitrary picture with the horizontal and vertical width defined by VERWIDTH and HORWIDTH at the position defined by VERPOS and HORPOS VERtical POSition defines the number of lines from the first active line to the first active line of an inserted picture VERtical WIDTH defines the number of lines (vertical width) of an inserted picture HORizontal POSition defines the number of pixels from the first active pixel to the first active pixel of an inserted picture HORizontal WIDTH defines the number of pixels (horizontal width) of an inserted picture
05h 00h
08h
07h 0Ah
09h
Inside the SDA 9401 a field detection block is necessary for the detection of an odd (A) or even (B) field. Therefore the incoming H-Sync H1 (delayed HIN signal, delay depends on NAPIPDL and NAPIPPH) is doubled (H2 signal). Depending on the phase position of the rising edge of the VIN signal an A (rising edge between H1 and H2) or B (rising edge between H2 and H1) field is detected. For proper operation of the field detection block, the VIN must be delayed depending on the delay of the HIN signal (H1). The figure below explains the field detection process and the functionality of the VINDEL parameter (inside the SDA 9401 the delayed VIN signal is called Vd and the detected field signal is called Ffd).
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Preliminary Data Sheet
SDA 9401
Field detection and VIN delay
CLK1 H1 H2 VIN Vd Ffd
x
(VINDEL * 128 + 1) * Tclk1
Field 1(A)
VIN Vd Ffd
x
(VINDEL * 128 + 1) * Tclk1
Field 2(B)
Input write parameter
Parameter [Default value] Subaddress Description
VINDEL [0] FIEINV 1: Field A=1 0: Field A=0 [0] VCRMODE 1: on 0: off [1]
01h 00h
Delay of the incoming V-Sync VIN (must be adjusted depending on the delay of the HIN signal) Inversion of the internal field polarity
00h
In case of non standard interlaced signals (VCR, PlayStations) a filtering of the internal field signal can be done (can also be used for normal TV signals)
In case of non-standard signals the field order is indeterminate (e.g. AAA... , BBB... , AAABAAAB..., etc.). Therefore a special filtering algorithm is implemented, which can be switched on by the parameter VCRMODE. The OPDEL parameter is used to adjust the outgoing V-Sync VOUT in relation to the incoming delayed V-Sync VIN. In case of 50 Hz to 100 Hz interlaced scan rate conversion the OPDEL parameter should be greater than half the number of lines of a field plus the internal processing delay (8 lines).
Input write parameter
Parameter [Default value] Subaddress Description
OPDEL [170]
06h
Delay (in number of lines) of the internal V-Sync (delayed VIN) to the outgoing V-Sync (VOUT)
The internal line counter is used to determine the information about the standard of the incoming
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Preliminary Data Sheet
fielddet
SDA 9401
signal. Input read parameter
Parameter Subaddress Description
TVMODE
33h
TV standard of the incoming signal: 1: NTSC 0: PAL
The figure below shows applications of the picture insert mode. For this feature an additional PIP circuit (e.g. SDA 9388, SDA 9488/89) is necessary. Together with the PIP IV circuit (SDA 9488/89) also split screen applications like double window are possible. The compression of the inserted picture has also be done by the external PIP or front-end processor. Picture insert mode: application examples picture tracking, random pictures
6.2
Input format conversion (IFC)
Input signals
Signals Pin number Description
YIN0...7 UVIN0...7
43, 44, 45, 46, 47, 48, 49, 50 31, 32, 33, 34, 37, 38, 39, 40
luminance input chrominance input
The SDA 9401 accepts at the input side the sample frequency relations of Y : (B-Y) : (R-Y): 4:2:2 and CCIR 656. In case of CCIR 656 three modes are supported (FORMAT=11 means full CCIR 656 support, including H-, V-Sync and Field signal, FORMAT=01 means only data processing, H- and V-Sync have to be added separately according PAL/NTSC norm, FORMAT=10 means only data processing, H- and V-sync have to be added separately according CCIR656-PAL/NTSC norm). The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, parameter TWOIN=0) or two's complement code (TWOIN=1, see also chapter IC bus format on page 45, IC bus parameter 00h). Inside the SDA 9401 all algorithms assume positive dual code.
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Preliminary Data Sheet
track01
SDA 9401
Input data formats Data Pin YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 UVIN7 UVIN6 UVIN5 UVIN4 UVIN3 UVIN2 UVIN1 UVIN0 CCIR 656 FORMAT = 1X FORMAT = 01 U07 U06 U05 U04 U03 U02 U01 U00 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 V07 V06 V05 V04 V03 V02 V01 V00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 4:2:2 Parallel FORMAT = 00
Xab: X: signal component a: sample number b: bit number
Input sync formats
FORMAT HIN VIN YIN UVIN
00 01 (CCIR 656 only data) 10 11 (full CCIR 656)
PAL/NTSC PAL/NTSC CCIR 656 x
PAL/NTSC PAL/NTSC CCIR 656 x
4:2:2 CCIR 656 CCIR 656 CCIR 656
4:2:2 x x x
The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 27 MHz. Consequently the SDA 9401 is dedicated for application in high quality digital video systems. The figure below shows the generation of the internal H- and V-syncs in case of full CCIR 656 mode. The H656 sync is generated after the EAV. The V656 and F656 signals change synchronously with the EAV timing reference code.
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Preliminary Data Sheet
SDA 9401
Explanation of 656 format
CLK1 (27 MHz) CCIR 656 interface YIN
EAV SAV u0 y0 v0 y1 u2 y3 EAV
288 Tclk1(PAL) 276 Tclk1(NTSC) 1728 Tclk1(PAL) 1716 Tclk1(NTSC)
CLK1 (27 MHz) YIN H656 V656 (e.g.) F656 (e.g.)
EAV 11111111 00000000 00000000 1FV1P3P2P1P0 x EAV x x SAV x x EAV x
F = 0 during field 1(A) F = 1 during field 2(B)
MSB
LSB
SAV 11111111 00000000 00000000 1FV0P3P2P1P0
V = 0 elsewhere V = 1 during field blanking
The figure below explains the functionality of the SYNCEN signal. The SDA 9401 needs the SYNCEN (synchronization enable) signal, which is used to gate the YIN, UVIN as well as the HIN and the VIN signal. This is implemented for front-ends which are working with 13.5 MHz and a large output delay time for YIN, UVIN, HIN and VIN (e.g. Micronas VPC32XX, output delay: 35 ns). For this application the half system clock CLK1 (13.5 MHz) from the front-end should be provided at this pin. In case the front-end is working at 27.0 MHz with sync signals having delay times smaller than 25 ns, this input can be set to low level (SYNCEN=VSS) (e.g. Micronas SDA 9206, output delay: 25 ns). Thus the signals YIN, UVIN, HIN and VIN are sampled with the CLK1 system clock when the SYNCEN input is low. SYNCEN signal
CLK1 SYNCEN YIN UVIN YINen UVINen HIN/VIN HINen/VINen
x x y0 u0 y1 v0 y2 u2 y3 v2
x x
y0 u0
y1 v0
y2 u2
y3 v2
syncen
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Preliminary Data Sheet
SDA 9401
The figure below shows the input timing and the functionality of the NAPIPDL and NAPIPPH parameter in case of CCIR 656 and 4:2:2 parallel data input format for one example. The signals HINint, YINint and UVint are the internal available sampled input signals. Input timing
CLK1 HIN HINint CCIR 656 interface YIN
xxx u0 y0 u0 y0 u0 v0 y1 v0 y1 v0 u2 y2 u2 y2 u2 v2 y3 v2 y3 v2 u4 y4 u4
(NAPIPDL* 4 + NAPIPPH + 7) * Tclk1 =(0 * 4 + 2 + 7) * Tclk1 = 9 Tclk1 (e.g.) YINint UVINint 4:2:2 interface YIN UVIN YINint UVINint
xxx xxx y0 u0
(NAPIPDL* 4 + NAPIPPH + 7) * Tclk1 =(0 * 4 + 3 + 7) * Tclk1 = 10 Tclk1 (e.g.)
y1 v0 y0 u0
y2 u2 y1 v0
y3 v2 y3 u2
y4 u4 y4 v2
ifc01
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Preliminary Data Sheet
SDA 9401 6.3 Low data rate processing
The next figure shows the block diagram of the low data rate processing block. The input signal can be vertically and horizontally compressed by a limited number of factors. In case of multipicture mode the internal Multipicture controller will use both compression blocks to control the different modes. Furthermore the input signal can be processed by different noise reduction algorithms to reduce the noise in the signal. The noise measurement block determines the noise level of the input signal. Block diagram of low data rate processing
NMLINE, NMALG NOISEME MULTIPIC, PICPOS, YBORDER, UBORDER, VBORDER
Noise measurement
Multipicture controller
YIN UVIN
Line memories
Vertical compression
Horizontal compression
Spatial noise reduction
Temporal noise reduction
VDECON, VCSNRON
HDECON, HCSNRON
SNRON
NRON
The different blocks and the corresponding parameters will be described now in more detail.
6.3.1
Vertical compression
The vertical compression compresses the incoming signal vertically by a constant factor given by the parameter VDECON. For the Y and UV signal different filter characteristics are used. The vertical compression can be switched off. For the multipicture modes the factors VDECON 2, 3 and 4 are necessary. Different filter characteristics are used for the factors 3 and 4. High quality vertical compression for double window applications is possible, because the filter characteristic is optimized for the factor 1.5. The table below shows the relation between the parameter VDECON and the compression factor.
Input write parameter: VDECON
VDECON (1Ch)
0 1 2 3 4 5 6 7
Vertical compression off Factor 1.25 Factor 1.5 Factor 1.75 Factor 2.0 Factor 3.0 Factor 4.0 not defined
Inside the SDA 9401 the number of active lines per field depends on the chosen vertical compression factor VDECON (see also chapter Output sync controller (OSC) on page 29).
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Preliminary Data Sheet
bdldr01 Y from Memory Y to Memory UV to Memory UV from Memory
SDA 9401 6.3.2 Horizontal compression
The horizontal compression compresses the incoming signal horizontally by a constant factor. For the Y and UV signal the same filter characteristics are used. The horizontal compression can be switched off. The table below shows the relation between the parameter HDECON and the compression factor.
Input write parameter: HDECON
HDECON (1Ch)
00 01 10 11
no horizontal compression factor 2 factor 4 not defined
The APPLIP (Active Pixels Per Line Input, see also chapter Input sync controller (ISC) on page 9) value defines the length of an active line. Inside the SDA 9401 the number of active pixels per line is APPL (Active Pixels Per Line) and its value depends on the chosen horizontal compression factor HDECON. The table below explains the connection between APPL and APPLIP (see also chapter Output sync controller (OSC) on page 29). Connection between APPL and APPLIP
Mode APPL
no horizontal compression (HDECON = '00') horizontal compression, Factor 2 (HDECON = '01') horizontal compression, Factor 4 (HDECON = '10') MULTIPIC > '0' (dominant, see also chapter page 18)
APPLIP (APPLIP + 1) / 2 (APPLIP + 3) / 4 45
Multipicture display on
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Preliminary Data Sheet
SDA 9401 6.3.3 Multipicture display
The figures below show the different "multi picture modes" as they are represented on the display. Fourfold multi picture
PICPOS =0 PICPOS =1
PICPOS =2
PICPOS =3
Twelvefold multi picture
PICPOS=0 PICPOS=1 PICPOS=2 PICPOS=3
PICPOS=4
PICPOS=5
PICPOS=6
PICPOS=7
PICPOS=8
PICPOS=9
PICPOS=10
PICPOS=11
Sixteenfold multi picture
P I C PO S = 0 PI C P OS = 1 PI C P O S= 2 PI C P OS = 3
P I C PO S = 4
PI C P OS = 5
PI C P O S= 6
PI C P OS = 7
P I C PO S = 8
PI C P OS = 9
PI C PO S = 10
PI C P OS = 11
P I C PO S = 12
PI C P OS = 13
PI C PO S = 14
PI C P OS = 15
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Preliminary Data Sheet
SDA 9401
The three different "multi picture modes" can be selected by the parameter MULTIPIC. MULTIPIC=0 defines normal operation without compression. The table below explains the performed compressions depending on the "multi picture mode" and the corresponding aspect ratio of the display.
Input write parameter: MULTIPIC
MULTIPIC (1Bh) Horizontal compression Vertical compression Aspect ratio of the display
00 (Multi Picture Off) 01 (fourfold) 10 (twelvefold) 11 (sixteenfold) 2:1 4:1 4:1
normal operation, no compression
2:1 4:3 16 : 9 4:3
3:1 4:1
To get a "multi picture display" the following executions must be performed: Entering a "multi picture mode" is defined by transmitting a value MULTIPIC>0. This value of MULTIPIC must not be equal to the previous value of MULTIPIC. During the following two fields the memory will be completely filled with a constant colour defined by the parameters YBORDER, UBORDER, VBORDER. This colour is identical to the background and the borders of the multi picture display. The same procedure is performed when the "multi picture mode" changes from a value MULTIPIC>0 to another value MULTIPIC>0. Beginning with the following field the compressed input picture is written at the position PICPOS addressed via IC-bus. The user has to address all possible positions PICPOS one after the other to build a complete multi picture display. In sequence, the background colour is replaced by the small pictures. The not overwritten areas of the background colour form the borders of the multi picture display. The pictures can be taken from the same source ('Shots of a Sequence') or from different sources ('Tuner Scanning'). The actual addressed picture is moving until "Freeze mode" is activated. Before entering "multi picture mode" the "H-and-V-freerunning mode" (see also chapter Output sync controller (OSC) on page 29) should be activated via the IC bus bits HOUTFR and VOUTFR, especially when "Tuner Scanning" will be performed. The "H-and-V-freerunning mode" avoids synchronization problems of the display during changing the tuner channel. The values of ALPFIP (Active Lines Per Field Input, see also chapter Input sync controller (ISC) on page 9), and ALPFOP (Active Lines Per Field Output, see also chapter Output sync controller (OSC) on page 29) must be set to 144 or 121, respectively. Only these standard signals corresponding to PAL and NTSC systems are supported. A mixture of PAL and NTSC signals is also possible. Input write parameter
Parameter Subaddress Description
MULTIPIC PICPOS YBORDER UBORDER VBORDER Micronas
1Bh 1Bh 17h 18h 18h
Defines the multi picture modes Position of the picture in the multi picture mode (only valid for MULTIPIC>0) Y background value U background value V background value 19 Preliminary Data Sheet
SDA 9401
Parameter
Subaddress
Description
FREEZE 1: on 0: off
1Bh
Freeze mode (frozen picture)
Interlaced conversion in multi picture mode
STOPMODE RMODE Raster Sequence Comment fixed
0110 (AAAA mode)
0
(100/120 Hz)
The borders are fixed to a width of 16 pixels in horizontal direction. In vertical direction the border widths are also fixed, the number of lines, however, depends on the TV standard of the input and the display.
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Preliminary Data Sheet
SDA 9401 6.3.4 Noise reduction
The figure below shows a block diagram of the spatial and temporal motion adaptive noise reduction (first order IIR filter). The spatial noise reduction of the luminance differs from the spatial noise reduction of the chrominance. The structure of the temporal motion adaptive noise reduction is the same for the luminance as for the chrominance signal. Block diagram of noise reduction
SNRON
YR YIN TNRCLY, TNRHOY, TNRKOY, TNRVAY, TNRFIY, NRON TNRCLC, TNRHOC, TNRKOC, TNRVAC, TNRFIC, NRON UVIN Spatial noise reduction YSNR DY Motion detector KY Field delay
Motion detector DUV Spatial noise reduction
KUV 1 0 TNRSEL Field delay
UV1
VCSNRON, HCSNRON
6.3.4.1
Spatial noise reduction
Normally a spatial noise reduction reduces the resolution due to the low pass characteristic of the used filter. Therefore the spatial noise reduction of the SDA 9401 works adaptive on the picture content. The low pass filter process is only executed on a homogeneous area. That's why an edge detection controls the low pass filter process and depending on the result of the edge detection the pixels for the low pass filter are chosen. The next figure shows a block diagram of the spatial noise reduction. For the UV signal only a simple spatial noise reduction algorithm (vertical and/or horizontal low pass filtering) is implemented.
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Preliminary Data Sheet
nr01
UVSNR
SDA 9401
Block diagram of spatial noise reduction
SNRON
YIN
LM
0 LP 1
YSNR
LM
Edge detection nr02
LM
UVIN
LM
LP
1 LP 0
1 UVSNR 0
VCSNRON
HCSNRON
Input write parameter
Parameter Subaddress Description
SNRON 1: on 0: off VCSNRON 1: on 0: off HCSNRON 1: on 0: off
1Dh
Spatial noise reduction of luminance signal
1Dh
Vertical spatial noise reduction of chrominance
1Dh
Horizontal spatial noise reduction of chrominance
In case of VDECON>0 or HDECON>0 or MULTIPIC>0 (see also chapter Vertical compression on page 16, see also chapter Horizontal compression on page 17, see also chapter Multipicture display on page 18) spatial noise reduction is not possible.
6.3.4.2
Motion adaptive temporal noise reduction
The equation below describes the behaviour of the temporal adaptive noise reduction filter. The same equation is valid for the chrominance signal. Depending on the motion in the input signal, the K-factor Ky (Kuv) can be adjusted between 0 (no motion) and 15 (motion) by the motion detector. The K-factor for the chrominance filter can be either Ky (output of the luminance motion detector, TNRSEL=0) or Kuv (output of the chrominance motion detector, TNRSEL=1).
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Preliminary Data Sheet
SDA 9401
Equation for temporal noise reduction (luminance signal)
1 + Ky YOUT = ae --------------- o YSNR - YR + YR e 16
Equation for temporal noise reduction (chrominance signal)
1+K UVOUT = ae ------------ o UVSNR - UV1 + UV1 ;K = Ky ;Kuv e 16
The next figure shows the motion detector in more detail. Temporal noise reduction can be switched off by NRON (NRON=0). The parameter TNRFIY/C switches between a fixed noise reduction Kfactor TNRVAY/C (TNRFIY/C=0) or a motion adaptive noise reduction K-factor (TNRFIY/C=1). Block diagram of motion detector
TNRCLY/C+1 TNRKOY/C+1 TNRFIY/C NRON
Motion DY/UV Motion detection LUT
0 1
MUX
0
1
MUX 15
0
Ky/uv nr01
TNRHOY/C TNRVAY/C
In case of adaptive noise reduction the K-factor depends on the detected "Motion" (see figure above). The "Motion"-Ky/Kuv characteristic curve (LUT) is fixed inside the SDA 9401, but the characteristic curve can be changed by two parameters: TNRHOY/C and TNRKOY/C. TNRHOY/C shifts the curve horizontally and TNRKOY/C shifts the curve vertically. For a fixed characteristic curve, the sensitivity of the motion detector is adjustable by TNRCLY/C. LUT for motion detection I
Ky/Kuv 15 TNRKOY/C=7 TNRHOY/C=0 TNRKOY/C=-1 TNRHOY/C=0 10 TNRKOY/C
5
TNRKOY/C=-8 TNRHOY/C=0
Motion 5 10 15 20 25 30
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Preliminary Data Sheet
nr02
SDA 9401
LUT for motion detection II
Ky/Kuv 15 TNRKOY/C=-1 TNRHOY/C=15 TNRKOY/C=-1 TNRHOY/C=0 10 TNRHOY/C TNRKOY/C=-1 TNRHOY/C=-15
5
Motion 5 10 15 20 25 30
Parameter TNRVAY/C
Parameter 0 (minimum value) 15 (maximum value)
TNRVAY/ C
strong noise reduction (not motion adaptive, Ky/K=0)
no noise reduction (not motion adaptive, Ky/K=15)
Parameter TNRHOY/C and TNRKOY/C
Parameter Range
TNRHOY/C TNRKOY/C
Parameter TNRCLY
Parameter
-32, ... , 31 -8, ..., 7
0 (minimum value)
15 (maximum value)
TNRCLY/ C
maximum sensitivity for motion -> strong noise reduction
minimum sensitivity for motion -> weak noise reduction
Input write parameter
Parameter Subaddress Description
TNRSEL 1: separate 0: luminance motion detector
1Dh
Switch for motion detection of temporal noise reduction of chrominance signal
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nr03
Preliminary Data Sheet
SDA 9401
Parameter
Subaddress
Description
TNRFIY/C 1: off 0: on TNRVAY/C TNRHOY/C TNRKOY/C TNRCLY/C
21h/22h
Switch for fixed K-factor value defined by TNRVAY/C
20h 21h/22h 1Fh 1Eh
Fixed K-factor for temporal noise reduction of luminance/chrominance Horizontal shift of the motion detector characteristic Vertical shift of the motion detector characteristic Classification of temporal noise reduction
6.3.5
Noise measurement
The noise measurement algorithm can be used to change the parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. This is done by the ICbus controller which reads the NOISEME value, and sends depending on this value different parameter sets to the temporal noise reduction registers of the SDA 9401. The NOISEME value can be interpreted as a linear curve from no noise (0) to strong noise (30). Value 31 indicates an overflow status and can be handled in different ways: strong noise or measurement failed. Two measurement algorithms are included, which can be chosen by the parameter NMALG. In case NMALG=1 the noise is measured during the vertical blanking period in the line defined by NMLINE. For NMALG=0 the noise is measured during the first active line. In both cases the value is determined by averaging over several fields. The figure below shows an example for the noise measurement. The NMLINE parameter determines the line, which is used in the SDA 9401 for the measurement. In case of VINDEL=0 and NMLINE=0 line 3 of the field A and line 316 of the field B is chosen. In case of VINDEL=0 and NMLINE=3 line 6 of the field A and line 319 of the field B is chosen.
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Preliminary Data Sheet
SDA 9401
Example of noise measurement
623 H-sync V-sync 624 625 Field1 (A) 1 2 3 4 5 6 7
VINDEL=0 Measure NMLINE=0 NMLINE=3
: :
Measure
310 H-sync V-sync
311
312
Field2 (B) 313-1
314-2
315-3
316-4
317-5
318-6
319-7
VINDEL=0 Measure NMLINE=0 NMLINE=3
: :
Measure
PAL
Input write parameter
Parameter Subaddress Description
NMALG
1Dh
NMLINE
28h
Noise measurement algorithm 1: measurement during vertical blanking period (measure line can be defined by NMLINE) 0: measurement in the first active line Line for noise measurement (only valid for NMALG=1)
Input read parameter
Parameter Subaddress Description
NOISEME NMSTATUS
32h 33h
Noise level of the input signal: 0 (no noise), ... , 30 (strong noise) [31 (strong noise or measurement failed)] Signals a new value for NOISEME 1: a new value can be read 0: current noise measurement not finalized (see also chapter IC bus format on page 45)
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Preliminary Data Sheet
NM01
SDA 9401 6.4 Clock concept
Input signals
Signals Pin number Description
CLK1 X1/CLK2
54 28
System clock 1 input System clock 2 input
Output signals
Signals Pin number Description
CLKOUT
26
Clock output
The SDA 9401 supports different clock concepts. In chapter 10 (see also chapter Application information on page 65) a typical application of the circuit is shown. The front-end clock is connected to CLK1 input. The CLKOUT pin is connected to the back-end and the X1/CLK2 input is connected to a crystal oscillator. The next figure explains the different clock switches, which may be used for the separate modes (see also page 31, "Ingenious configurations of the HOUT and VOUT generator"). Clock concept
cloco CLKOUT
CLK1
PLL1
CLK1_pll1
1 X1/CLK2
PLL2
0 1 CLK2_pll2 CLK11EN
0
CLK21EN
Clock concept switching matrix
CLK11EN (19h) CLK21EN (19h) CLKOUT
0 0 1
1 0 X
CLK1 not allowed CLK2_pll2
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Preliminary Data Sheet
SDA 9401
Clock
Used in block
CLK1_pll1 CLK2_pll2
ISC, IFC, LDR, ED, MC, LM, IC OSC, HDR, ED, MC, LM, OFC
Input write parameter
Parameter Subaddress Description
PLL1OFF 1: off 0: on PLL1RA PLL2OFF 1: off 0: on PLL2RA CLKOUTON 1: enabled 0: disabled
02h
PLL 1 on or off
09h,0Ah 16h
PLL range, only for test purposes PLL 2 on or off
19h 16h
PLL range, only for test purposes Output of system clock
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Preliminary Data Sheet
SDA 9401 6.5 Output sync controller (OSC)
Output signals
Signals Pin number Description
HOUT
60
VOUT
61
HREF INTERLACED
62 18
horizontal synchronization signal (polarity programmable, IC bus parameter 14h HOUTPOL, default: high active) vertical synchronization signal (polarity programmable, IC bus parameter 14h VOUTPOL, default: high active) horizontal active video output interlaced signal (can be used for AC coupled deflection circuits)
The output sync controller generates horizontal and vertical synchronization signals for the scan rate converted output signal. The figures below show the block diagram of the OSC and the existing parameters. Block diagram of OSC
HOUTPOL, HOUTFR, APPLOP, HOUTDEL, NAPOP, PPLOP
HIN VIN
OPERATION mode generator
HOUT generator
HOUT HREF VOUT INTERLACED
WINDOW generator
VOUT generator
STOPMODE
VOUTPOL, INTMODE, NALOP, ALPFOP, LPFOP
WINDVON, WINDVDR, WINDVSP, WINDVST, WINDHON, WINDHDR, WINDHSP, WINDHST
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osc01
Preliminary Data Sheet
SDA 9401
Output parameter
HOUT (PPLOP*2)*CLK2 VOUT
(NALOP+1)*2
LPFOP*4+1
(ALPFOP*4)
(NAPOP*4)*CLK2
(APPL*16)*CLK2
(HOUTDEL*4+1)*CLK2
(APPLOP*16)*CLK2
Output write parameter
Parameter [Default value] Subaddress Description
NALOP [22] ALPFOP [144] LPFOP [156] HOUTDEL [4] NAPOP [0] APPLOP [45] APPL
0Bh 0Ch 0Dh 0Fh 0Eh 10h internal
PPLOP [432]
11h, 12h
Not Active Line OutPut defines the number of lines from the V-Sync to the first active line of the output frame Active Lines Per Field OutPut defines the number of active lines per output frame Lines Per Frame OutPut defines the number of lines per output frame (only valid for VOUTFR=1) HOUT DELay defines the number of pixels from the HSync to the first active pixel Not Active Pixel OutPut defines the number of not active pixels (e.g. coloured border values) Active Pixels Per Line OutPut defines the number of pixels per line including border pixels Active Pixels Per Line defines the number of active pixels (see also Horizontal compression on page 17, APPLIP) Pixel Per Line OutPut defines the number of pixels between two consecutive H-Syncs (only valid for HOUTFR=1)
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inpar01
Preliminary Data Sheet
SDA 9401
The next paragraphs describe the HOUT and VOUT generator in more detail. Both generators have a so called "locked-mode" and "freerunning-mode". Not all combinations of the modi make sense. The table below shows ingenious configurations.
Ingenious configurations of the HOUT and VOUT generator
Mode HOUTFR VOUTFR CLK11EN CLK21EN
"H-and-V-locked" "H-freerunning-V-locked" "H-and-V-freerunning"
0 1 1
0 0 1
1 1 1
1 0 0
6.5.1
HOUT generator
The HOUT generator has two operation modes, which can be selected by the parameter HOUTFR. The HOUT signal is active high (HOUTPOL=0) for 64 clock cycles (X1/CLK2). In the freerunningmode the HOUT signal is generated depending on the PPLOP parameter. In the locked-mode the HOUT signal is locked on the incoming H-Sync signal HIN. The polarity of the HOUT signal is programmable by the parameter HOUTPOL. The HREF signal marks the active part of a line. The figure below shows the timing relation of the HOUT and the HREF signal. The distance is programmable by the parameter HOUTDEL. PD means processing delay of the internal data processing (PD=36 X1/CLK2 clocks). The length of the active part is determined by the parameter APPLOP. If the number of the active pixels (internal parameter APPL, see also Horizontal compression on page 17) is smaller than the number of the displayed pixels (e.g. displaying a 4:3 source on a 16:9 screen), a coloured border can be defined using the NAPOP parameter. The border colour is defined by the parameters YBORDER, UBORDER and VBORDER. To avoid transition artifacts of digital filters the number of active pixels per line (parameter APPL) can be symmetrically reduced using the CAPP parameter. The figure below shows also the internal signal ALOP, which marks the active pixels of the line.
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Preliminary Data Sheet
SDA 9401
Timing diagram of output signals
X1/CLK2 HOUT
64 * Tx1/clk2 PPLOP * 2 Tx1/clk2 e.g. 432 * 2 / 27 MHz = 32 s
YOUT UVOUT
x x
y0 u0
y1 v0
y2 u2
y3 v2
y4 u4
y5 v4
ym-2 ym-1 um-2 vm-2
x x
m=APPL*16 ((HOUTDEL + 1) * 4 + PD)* Tx1/clk2
outpar01
HREF
APPLOP * 16 * Tx1/clk2 e.g. 45 * 16 = 720 Tx1/clk2 YOUT UVOUT
x x YB UB YB VB YB UB YB VB y0 u0 y1 v4 YB UB YB VB x x
m=APPL*16 ((HOUTDEL + 1 + NAPOP) * 4 + PD)* Tx1/clk2 ALOP
Output write parameter
Parameter Subaddress Description
HOUTFR 1: freerun 0: locked mode YBORDER UBORDER VBORDER CAPP 00: k = 0 01: k = 8 10: k = 16 11: k = 24
14h
HOUT generator mode select
17h 18h 18h 10h
Y border value (four MSB of the 8 bit colour) U border value (four MSB of the 8 bit colour) V border value (four MSB of the 8 bit colour) Reducing factor for the Active Pixels Per Line Value (APPL) Number of active pixels per line = 16 * APPL - 2*k
6.5.2
VOUT generator
The VOUT generator has two operation modes, which can be selected by the parameter VOUTFR. The VOUT signal is active high (VOUTPOL=0) for two output lines. In the freerunning-mode the VOUT signal is generated depending on the LPFOP parameter. In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal VIN (means the internal VIN delayed by the parameter OPDEL, see also Input sync controller (ISC) on page 9). The RMODE parameter (raster mode 1: progressive, 0: interlaced) determines the scan rate conversion
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Preliminary Data Sheet
SDA 9401
mode. The figure below shows the two cases. If RMODE=1, then for each incoming V-sync signal VIN an outgoing V-sync signal VOUT has to be generated (50 Hz interlaced to 50 Hz progressive scan rate conversion). If RMODE=0, then during one incoming V-Sync signal, two VOUT pulses have to be generated (50 Hz interlaced to 100 Hz interlaced scan rate conversion). Examples for VOUT generation depending on parameter RMODE
VIN RMODE=1 VOUT
RMODE=0 VOUT
The VOUT signal has a delay of two CLKOUT clocks to the HOUT signal or in case of interlaced a delay of a half line plus two CLKOUT clocks.
Output write parameter
Parameter Subaddress Description
VOUTFR 1: freerun 0: locked mode RMODE 1: progressive 0: interlaced
14h
VOUT generator mode select
14h
Raster mode
Switching from H-and-V-freerunning to H-and-V-locked mode In H-and-V-freerunning mode, generally, the phase of the generated synchronization raster has no correlation to the input raster. A hard switch from the H-and-V-freerunning mode to the H-and-Vlocked mode therefore would cause visible synchronization artefacts. To avoid these problems the SDA 9400 enlarges the line and the field lengths of the output sync signals HOUT and VOUT in a defined procedure to enable an unvisible synchronization of the freerunning output to the input. For vertical synchronization the maximum synchronization time is 260 ms for interlaced and 520 ms for progressive display modes. Horizontal synchronization is performed in a maximum time of 50 ms. To get the best performance it is recommended to change at first the vertical and after the mentioned delay times the horizontal mode from free running to locked.
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Preliminary Data Sheet
SDA 9401 6.5.3 Operation mode generator
The VOUT generator determines the VOUT signal. For proper operation of the VOUT generator information about the raster sequence is necessary. The parameter STOPMODE (Static operation mode) defines the raster sequence and the scan rate conversion algorithm. The figure below explains the used wording for the following explanations. Explanations of field and display raster
FRAME/FIELD
FRAME FIELD A odd lines
FIELD B even lines
Content of picture
DISPLAY RASTER
TV Display raster odd lines Display raster
even lines
Display raster
Tube, Display raster
The interlaced input signal (e.g. 50 Hz PAL or 60 Hz NTSC) is composed of a field A (odd lines) and a field B (even lines). An - Input signal, field A at time n, Bn - Input signal, field B at time n The field information describes the picture content. The output signal, which could contain different picture contents (e.g. field A, field B ) can be displayed with the display raster or .
(An,) - Output signal, field A at time n, displayed as raster
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34
Preliminary Data Sheet
SDA 9401
(An,) - Output signal, field A at time n, displayed as raster
(An Bn-1,+==Output signal, frame AB at time n, progressive
((A*)n,) - Output signal, field A raster interpolated into field B at time n, displayed as raster
The table below describes the different scan rate conversion algorithms and the corresponding raster sequences. The delay between the input field and the corresponding output fields depends on the OPDEL parameter and the default value for the delay is an half input field. The INTERLACED signal can be used for AC-coupled deflections. Depending on the parameter INTMODE the value of this signal will be generated. The table below shows also the definition of this signal. Explanation of operation mode timing
osc02 Input fields
An
Bn
time
Fields available in the internal field stores
An-1, Bn-1
Bn-1, An
An, Bn
Output fields
OPDEL lines
an
Phase 0
bn
Phase 1
cn
Phase 2/0
dn
Phase 3/1
Static operation modes
Input field A STOPMODE Scan rate conversion algorithm Output n field a phase 0 Output n field b phase 1 Input field B Output n field c phase 2/0 Output n field d phase 3/1 RMODE
0000 0001 0010 0100 0101 0110 0111 1000 Micronas
not defined AA*B*B mode I interlaced AABB mode I interlaced Multipicture mode I Multipicture mode II AAAA mode BBBB mode not defined
x (A*)n,
INTMODE(3)
x An,
INTMODE(0)
x Bn,
INTMODE(1)
x (B*)n,
INTMODE(2)
0 0 0 0 0 0 0 0
An,
INTMODE(0)
An,
INTMODE(0)
Bn,
INTMODE(1)
Bn,
INTMODE(1)
An,
INTMODE(0)
An,
INTMODE(0)
An,
INTMODE(0)
An,
INTMODE(0)
Bn-1,
INTMODE(1)
Bn-1,
INTMODE(1)
Bn,
INTMODE(1)
Bn,
INTMODE(1)
An,
INTMODE(0)
An,
INTMODE(0)
An,
INTMODE(0)
An,
INTMODE(0)
Bn-1,
INTMODE(0)
Bn-1,
INTMODE(0)
Bn,
INTMODE(0)
Bn,
INTMODE(0)
x 35
x
x
x
Preliminary Data Sheet
SDA 9401
Input field A STOPMODE Scan rate conversion algorithm Output n field a phase 0 Output n field b phase 1
Input field B Output n field c phase 2/0 Output n field d phase 3/1 RMODE
1001 1010 1011,11xx 0000 0001 0010 0101 0111
AA*B*B mode II interlaced AABB mode II interlaced not defined not defined AA* mode I progressive not defined AA* mode II progressive B*B mode progressive not defined Test Mode (motion adaptive mode interlaced, DL) not defined
(B*)n-1,
INTMODE(2)
Bn-1,
INTMODE(1)
An+1,
INTMODE(0)
(A*)n+1,
INTMODE(3)
0 0 0 1 1
Bn-1,
INTMODE(1)
Bn-1,
INTMODE(1)
An+1,
INTMODE(0)
An+1,
INTMODE(0)
0011,0100, 0110 1000
x x (An A*n, ) x (An A*n, ) (Bn-1 B*n-1, ) x An A*n ) x
x x
x x (B*n Bn, ) x (An A*n, ) (Bn B*n, ) x B*n Bn, a+b/ ) x
x x
x
x
1 1 1
x
x
1 1
1xxx
x
x
1
The table below shows all possible display raster sequences for the different static operation modes and the line per field value between two consecutive output V-Syncs. It is assumed, that in case of freerunning-mode LPFOP=156 and in the locked mode the number of lines of the incoming field is 312.5.
Display raster sequence for RMODE=1 (progressive)
Display raster sequence 1. to 2. 2. to 3. (1.)
625
625
Display raster sequence for RMODE=0 (interlaced)
Display raster sequence 1. to 2. 2. to 3. 3. to 4. 4. to 5.(1.)
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313 36
312
313 Preliminary Data Sheet
SDA 9401
Display raster sequence
1. to 2.
2. to 3.
3. to 4.
4. to 5.(1.)
test mode only)
313 312 313 625.5
312 312.5 312.5 624.5
313 313 312 625.5
312 312.5 312.5 624.5
Output write parameter
Parameter Subaddress Description
STOPMODE INTMODE
12h 13h, 14h
Static operation modes Free programmable INTERLACED signal for AC-coupled deflection stages
6.5.4
Window generator
The figures below show the functionality of the horizontal and/or vertical window function. The actual TV display can be overwritten with a constant value (defined by YBORDER, UBORDER, VBORDER), which is called "closing" or the constant value can be overwritten with the actual TV signal, which is called "opening". For the generation some parameters exist, which will be explained in more detail afterwards. Examples for window feature
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Preliminary Data Sheet
WINDOW
SDA 9401
The feature can be enabled by the parameter WINDHON/WINDVON. The parameter WINDHST/ WINDVST defines the status of the window (opened or closed). Closed means, that only a constant value is displayed, opened means, that the full TV is displayed. The parameter WINDHDR/ WINDVDR defines, what can be done with the window (open the window, close the window).
Output write parameter: WINDHST/WINDVST and WINDHDR/WINDVDR
WINDHST/ WINDVST Description WINDHDR/ WINDVDR Description
0 0 1 1
Window is closed Window is closed Window is opened Window is opened
0 1 0 1
open the window window remains closed window remains open close the window
With each enabling of the window function by the WINDHON/WINDVON parameter, the status of the window will be as defined by the table above, that means the WINDHST/WINDVST parameter is only once interpreted after enabling the window function. To change afterwards the status from "window is close" to "window is open" or vice versa only the WINDHDR/WINDVDR has to be toggled. If for example the status WINDHST/WINDVST=0 and the WINDHDR/WINDVDR=0 the window is closed and will be open after enabling the feature by setting the parameter WINDHON/ WINDVON=1. To close the window only the parameter WINDHDR/WINDVDR has to be set to 1. Again to open the window WINDHDR/WINDVDR has to be set to 0. For example: After switching on the TV set, the customer should see the window closed and afterwards the window should be opened. Therefore the WINDHST/WINDVST has to be set to "0", the WINDHDR/ WINDVDR has to be set to "1" and the WINDHON/WINDVON has to be set to "1". So the customer will see first a screen with a colour defined by the IC parameters YBORDER, UBORDER and VBORDER. Then the WINDHDR/WINDVDR has to be set to "0", that means the window will be open and the customer will see the chosen TV channel. The speed of closing or opening the window can be defined by the parameter WINDHSP/ WINDVSP. The tables below explain the using of these parameters.
Output write parameter: WINDHSP
time to close/ open (e.g. 720 active pixel, 10ms per output field)
windhsp
freerun mode
locked mode
00 01 10 Micronas
pplop/256 pplop/128 pplop/64 38
distance/512 distance/256 distance/128
~4s ~2s ~1s Preliminary Data Sheet
SDA 9401
windhsp
freerun mode
locked mode
time to close/ open (e.g. 720 active pixel, 10ms per output field)
11
pplop/32
distance/64
~0.5s
Distance: Number of pixels in system clocks X1/CLK2 between two output H-Syncs time to close = time(field) * number of active pixels / (distance/512) e.g. time to close = 10 ms * 720 / (864/512) = 4,26 s time to close = time(field) * number of active pixels / (pplop/128)
Output write parameter: WINDVSP
time to close/ open (e.g. 576 active lines, 10ms per output field)
windvsp
freerun mode
locked mode
00 01 10 11
lpfop/128 lpfop/64 lpfop/32 lpfop/16
lpfip/256 lpfip/128 lpfip/64 lpfip/32
~5s ~2s ~1s ~0.5s
LPFIP: Lines per field of the input signal - amount of lines between two input V-Syncs time to close = time(field(interlaced)/frame(progressive)) * number of active lines / (lpfip/256) e.g. time to close = 10 ms * 576 / (312/256) = 4.7 s time to close = time(field) * number of active lines / (lpfop/128) Output write parameter
Parameter Subaddress Description
WINDVON 1: on 0: off WINDVDR 1: close window 0: open window WINDVST 1: window is opened 0: window is closed WINDVSP Micronas
15h
Vertical window feature on or off
15h
Direction of the vertical window feature
15h
Status of the vertical window feature after enabling the window feature Speed of the vertical window feature 39 Preliminary Data Sheet
15h
SDA 9401
Parameter
Subaddress
Description
WINDHON 1: on 0: off WINDHDR 1: close window 0: open window WINDHST 1: window is opened 0: window is closed WINDHSP FLASHON 1: on 0: off
16h
Horizontal window feature on or off
16h
Direction of the horizontal window feature
16h
Status of the horizontal window feature after enabling the window feature Speed of the horizontal window feature Flash of the TV signal (after each output V-Sync the TV signal or the constant background value defined by YBORDER, UBORDER, VBORDER is displayed)
16h 17h
6.6
Output format conversion (OFC)
Output signals
Signals Pin number Description
YOUT0...7 UVOUT0...7
7, 6, 5, 4, 3, 1, 64, 63 17, 16, 15, 14, 13, 12, 11, 10
luminance output chrominance output
The SDA 9401 supports at the output side only the sample frequency relations of Y : (B-Y) : (R-Y): 4:2:2. The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, parameter TWOOUT=0) or two's complement code (TWOOUT=1, see also IC bus format on page 45, IC bus parameter 17h). Output data format Data Pin YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 4:2:2 Parallel Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10
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Preliminary Data Sheet
SDA 9401
Data Pin
4:2:2 Parallel V07 V06 V05 V04 V03 V02 V01 V00
UVIN7 U07 UVIN6 U06 UVIN5 U05 UVIN4 U04 UVIN3 U03 UVIN2 U02 UVIN1 U01 UVIN0 U00
X ab: X: signal component a: sample number b: bit number
6.7
High data rate processing (HDR)
The output signal can be vertically expanded. The expansion as well as the different scan rate conversion algorithms are processed in the HDR block. For the vertical expansion line memories are used. If the operation frequency X1/CLK2 is higher than 27 MHz plus 10%, the line memories will not work correctly any more. In this case only simple processing will be possible. Simple processing means, that the vertical expansion must be disabled. The table below defines the internal expansion factor ZOOM depending on the RMODE and VERINT parameter. Output write parameter: VERINT
VERINT RMODE ZOOM
IC-bus parameter IC-bus parameter
0 1
2*(VERINT+1) (VERINT+1)
The reachable expansion factors are listed in the table below in case of VDECON=0 and VDECON=2 (vertical compression of the input signal with factor 1.0 and 1.5).
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Preliminary Data Sheet
SDA 9401
Examples of reachable expansion factors
100/120 Hz interlaced RMODE=0 VERINT 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 ZOOM 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 50/60 Hz progressive RMODE=1 ZOOM real vertical expansion factor VDECON=0 1.00 1.02 1.03 1.05 1.07 1.08 1.10 1.12 1.14 1.16 1.19 1.21 1.23 1.25 1.28 1.31 1.33 1.36 1.39 1.42 1.45 1.49 1.52 1.56 1.60 1.64 1.68 1.73 1.78 1.83 1.88 1.94 2.00 2.06 2.13 2.21 2.29 real vertical expansion factor VDECON=2 0.75 0.76 0.77 0.79 0.80 0.81 0.83 0.84 0.86 0.87 0.89 0.91 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.07 1.09 1.12 1.14 1.17 1.20 1.23 1.26 1.30 1.33 1.37 1.41 1.45 1.50 1.55 1.60 1.66 1.71
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Preliminary Data Sheet
SDA 9401
100/120 Hz interlaced RMODE=0 VERINT 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 ZOOM 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
50/60 Hz progressive RMODE=1 ZOOM
real vertical expansion factor VDECON=0 2.37 2.46 2.56 2.67 2.78 2.91 3.05 3.20 3.37 3.56 3.76 4.00 4.27 4.57 4.92 5.33 5.82 6.40 7.11 8.00 9.14 10.67 12.80 16.00 21.33 32.00 64.00
real vertical expansion factor VDECON=2 1.78 1.85 1.92 2.00 2.09 2.18 2.29 2.40 2.53 2.67 2.82 3.00 3.20 3.43 3.69 4.00 4.36 4.80 5.33 6.00 6.86 8.00 9.60 12.00 16.00 24.00 48.00
The parameter VPAN can be used to select the start line of the expansion. To expand the upper part of the incoming signal with the factor 2.0, VPAN should be set to zero. To expand the lower part, VPAN should be equal to 144. That means in case of VPAN=0 the first used line is line 1 and in case of VPAN=144 the first used line is line 144. Dependent on the parameter VERINT a certain number of input lines of the input field is required. Therefore not all VPAN values are allowed. The formula below can be used to calculate the maximum allowed VPAN value depending on the chosen VERINT value. Calculation of maximum VPAN value
VPANmax =
VERINT + 1 2 ALPFOP ae 1 - ----------------------------------- o e 64 43 Preliminary Data Sheet
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SDA 9401
Floor symbol means: take only integer part of x
x Output write parameter
Parameter Subaddress Description
VERINT VPAN
13h 1Ah
Vertical expansion factor Vertical adjustment of the output picture
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Preliminary Data Sheet
SDA 9401 6.8 6.8.1 IC bus IC bus slave address
Write Adress: BCh 10111100 Read Adress: BDh 10111101
6.8.2
IC bus format
The SDA 9401 IC bus interface acts as a slave receiver and a slave transmitter and provides two different access modes (write, read). All modes run with a subaddress auto increment. The interface supports the normal 100 kHz transmission speed as well as the high speed 400 kHz transmission. write:
S1 0 1 1 1 1 0 0 A
S: Start condition A: Acknowledge P: Stop condition NA: Not Acknowledge read:
Subaddress
A
Data Byte
A
*****
A
P
S1 0 1 1 1 1 0 0 A Data Byte NA P
Subaddress
AS1 0 1 1 1 1 0 1 A
Data Byte
A
The transmitted data are internally stored in registers. The master has to write a don't care byte to the subaddress FFh (store command) to make the register values available for the SDA 9401. To have a defined time step, where the data will be available, the data are made valid with the incoming V-sync VIN or with the next OPSTART pulse, which is an internal signal and indicates the start of a new output cycle. The subaddresses, where the data are made valid with the VIN signal are indicated in the overview of the subaddresses with VI", where the data are made valid with the OPSTART are indicated with OS". The IC parameter VISTATUS and OSSTATUS (subaddress 33h) reflect the state of the register values. If these bits are read as '0', then the store command was sent, but the data aren't made available yet. If these bits are '1' then the data were made valid and a new write or read cycle can start. The bits VISTATUS and OSSTATUS may be checked before writing or reading new data, otherwise data can be lost by overwriting. Furthermore the bit NMSTATUS (status of noise measurement: NOISEME). NMSTATUS signalizes a new value for NOISEME. So if NMSTATUS is read as '0' the current noise measurement has not
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Preliminary Data Sheet
SDA 9401
been finalized. If the NMSTATUS is read as '1' a new noise measurement value can be read. After switching on the IC, all bits of the SDA 9401 are set to defined states. Particularly :
Take over Take over
Subaddress
Default value
R/W
Subaddress
Default value
R/W
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
11h 00h 50h 90h 00h B4h AAh 00h 00h 00h 00h 16h 90h 9Ch 00h 04h B4h B0h 90h 3Fh 00h
W W W W W W W W W W W W W W W W W W W W W
VI VI VI VI VI VI VI VI VI VI VI OS OS OS OS OS OS OS OS OS OS
15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23...27 28 29...31 32 33 34...FE FF
00h 04h 14h 88h 0Ch 00h 00h 01h 03h FFh 00h FFh 02h 02h not used 22h not used
W W W W W W W W W W W W W W W R R
OS OS OS OS OS OS VI VI VI VI VI VI VI VI VI
not used W
R/W: R - Read Register; W - Write Register; R/W - Read and Write Register; Take over: VI - take over with VIN; OS- take over with OPSTART Reading the "Read only" register 32h must be followed by reading the "Read only" register 33h.
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Preliminary Data Sheet
SDA 9401 6.8.3 IC bus commands
Subadd. (Hex.) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 Data Byte D7
FORMAT1 ISC/IFC VINDEL5 ISC NALIP5 ISC ALPFIP7 ISC NAPIPDL7 ISC APPLIP5 ISC OPDEL7 ISC
D6
FORMAT0 ISC/IFC VINDEL4 ISC NALIP4 ISC ALPFIP6 ISC NAPIPDL6 ISC APPLIP4 ISC OPDEL6 ISC
D5
FIEINV ISC VINDEL3 ISC NALIP3 ISC ALPFIP5 ISC NAPIPDL5 ISC APPLIP3 ISC OPDEL5 ISC
D4
VCRMODE ISC VINDEL2 ISC NALIP2 ISC ALPFIP4 ISC NAPIPDL4 ISC APPLIP2 ISC OPDEL4 ISC
D3
PIMODE ISC VINDEL1 ISC NALIP1 ISC ALPFIP3 ISC NAPIPDL3 ISC APPLIP1 ISC OPDEL3 ISC
D2
NAPIPPH1 ISC VINDEL0 ISC NALIP0 ISC ALPFIP2 ISC NAPIPDL2 ISC APPLIP0 ISC OPDEL2 ISC
D1
NAPIPPH0 ISC VINPOL ISC PLL1OFF PLL1 ALPFIP1 ISC NAPIPDL1 ISC x OPDEL1 ISC
D0
TWOIN ISC/IFC HINPOL ISC REFRESH MC ALPFIP0 ISC NAPIPDL0 ISC x OPDEL0 ISC
VERWIDTH7 VERWIDTH6 VERWIDTH5 VERWIDT4 VERWIDTH3 VERWIDTH2 VERWIDTH1 VERWIDTH0 ISC ISC ISC ISC ISC ISC ISC ISC VERPOS7 ISC VERPOS6 ISC VERPOS5 ISC VERPOS4 ISC VERPOS3 ISC VERPOS2 ISC VERPOS1 ISC PLL1RA1 PLL1 PLL1RA3 PLL1 NALOP1 OSC ALPFOP1 OSC LPFOP1 OSC NAPOP1 OSC HOUTDEL1 OSC CAPP1 OSC PPLOP1 OSC 0 VERINT1 OSC VOUTPOL OSC 0 VERPOS0 ISC PLL1RA0 PLL1 PLL1RA2 PLL1 NALOP0 OSC ALPFOP0 OSC LPFOP0 OSC NAPOP0 OSC HOUTDEL0 OSC CAPP0 OSC PPLOP0 OSC 0 VERINT0 OSC HOUTPOL OSC 0
HORWIDTH5 HORWIDTH4 HORWIDTH3 HORWIDTH2 HORWIDTH1 HORWIDT0 ISC ISC ISC ISC ISC ISC HORPOS5 ISC NALOP7 OSC ALPFOP7 OSC LPFOP7 OSC NAPOP7 OSC HOUTDEL7 OSC APPLOP5 OSC PPLOP7 OSC PPLOP8 OSC INTMODE3 OSC INTMODE1 OSC WINDVON OSC HORPOS4 ISC NALOP6 OSC ALPFOP6 OSC LPFOP6 OSC NAPOP6 OSC HOUTDEL6 OSC APPLOP4 OSC PPLOP6 OSC HORPOS3 ISC NALOP5 OSC ALPFOP5 OSC LPFOP5 OSC NAPOP5 OSC HOUTDEL5 OSC APPLOP3 OSC PPLOP5 OSC HORPOS2 ISC NALOP4 OSC ALPFOP4 OSC LPFOP4 OSC NAPOP4 OSC HOUTDEL4 OSC APPLOP2 OSC PPLOP4 OSC HORPOS1 ISC NALOP3 OSC ALPFOP3 OSC LPFOP3 OSC NAPOP3 OSC HOUTDEL3 OSC APPLOP1 OSC PPLOP3 OSC HORPOS0 ISC NALOP2 OSC ALPFOP2 OSC LPFOP2 OSC NAPOP2 OSC HOUTDEL2 OSC APPLOP0 OSC PPLOP2 OSC 0 VERINT2 OSC HOUTFR OSC 0
STOPMODE3 STOPMODE2 STOPMODE1 STOPMODE0 OSC OSC OSC OSC INTMODE2 OSC INTMODE0 OSC WINDVDR OSC VERINT5 OSC 0 WINDVST OSC VERINT4 OSC RMODE OSC WINDVSP1 OSC VERINT3 OSC VOUTFR OSC WINDVSP0 OSC
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Preliminary Data Sheet
SDA 9401
16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 28 32 33 FF
WINDHON OSC
WINDHDR OSC
WINDHST OSC
WINDHSP1 OSC
WINDHSP0 CLKOUTON OSC PLL2 FLASHON OFC TWOOUT OFC
PLL2OFF PLL2 0
x 0
YBORDER3 YBORDER2 YBORDER1 YBORDER0 OFC/LDR OFC/LDR OFC/LDR OFC/LDR
UBORDER3 UBORDER2 UBORDER1 UBORDER0 VBORDER3 VBORDER2 VBORDER1 VBORDER0 OFC/LDR OFC/LDR OFC/LDR OFC/LDR OFC/LDR OFC/LDR OFC/LDR OFC/LDR PLL2RA3 PLL2 VPAN7 MC MULTIPIC1 LDR/ISC VDECON2 LDR NRON LDR/MC TNRCLY3 LDR TNRKOY3 LDR TNRVAY3 LDR TNRHOY5 LDR TNRHOC5 LDR NMLINE4 LDR NOISME4 LDR x x PLL2RA2 PLL2 VPAN6 MC MULTIPIC0 LDR/ISC VDECON1 LDR SNRON LDR TNRCLY2 LDR TNRKOY2 LDR TNRVAY2 LDR TNRHOY4 LDR TNRHOC4 LDR NMLINE3 LDR NOISME3 LDR x x PLL2RA1 PLL2 VPAN5 MC PICPOS3 LDR/MC VDECON0 LDR VCSNRON LDR TNRCLY1 LDR TNRKOY1 LDR TNRVAY1 LDR TNRHOY3 LDR TNRHOC3 LDR NMLINE2 LDR NOISEME2 LDR x x PLL2RA0 PLL2 VPAN4 MC PICPOS2 LDR/MC HDECON1 LDR/ISC HCSNRON LDR TNRCLY0 LDR TNRKOY0 LDR TNRVAY0 LDR TNRHOY2 LDR TNRHOC2 LDR NMLINE1 LDR NOISEME1 LDR TVMODE LDR x CLK21EN PLL2 VPAN3 MC PICPOS1 LDR/MC HDECON0 LDR/ISC 0 TNRCLC3 LDR TNRKOC3 LDR TNRVAC3 LDR TNRHOY1 LDR TNRHOC1 LDR NMLINE0 LDR NOISEME0 LDR VISTATUS x CLK11EN PLL2 VPAN2 MC PICPOS0 LDR/MC 0 0 TNRCLC2 LDR TNRKOC2 LDR TNRVAC2 LDR TNRHOY0 LDR TNRHOC0 LDR 0 VERSION2 OSSTATUS x 0 VPAN1 MC FREEZE MC 0 TNRSEL LDR TNRCLC1 LDR TNRKOC1 LDR TNRVAC1 LDR TNRFIY LDR TNRFIC LDR 1 VERSION1 x x 0 VPAN0 MC 0 1 NMALG LDR TNRCLC0 LDR TNRKOC0 LDR TNRVAC0 LDR 0 0 x VERSION0 NMSTATUS x
x = don't care ISC - Input sync controller block IFC - Input format conversion block OSC - Output sync controller block OFC - Output format conversion block LDR - Low data rate block HDR - High data rate block MC - Memory controller PLL1 - Clock doubling block 1 PLL2 - Clock doubling block 2
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Preliminary Data Sheet
SDA 9401 6.8.4 Detailed description
Default values are underlined.
Subaddress 00 Bit Name Function Input format: 11: full CCIR 656 10: CCIR 656 only data, H- and V-sync according CCIR656 01: CCIR 656 only data, H- and V-sync according PAL/NTSC 00: 4:2:2 Field polarity inversion: 1: Field A=1, Field B=0 0: Field A=0, Field B=1 Input filtering of the incoming field signal: 1: on 0: off Picture insert mode (see VERWIDTH, VERPOS, HORWIDTH, HORPOS): 1: on 0: off Number of not active pixels from external HIN to the input data in system clocks of CLK1: Number(HIN to input data) = (NAPIPDL*4+NAPIPPH+8) [NAPIPPH = 0] Chrominance input format: 1: 2's complement input (-128...127) 0: unsigned input (0...255) inside the SDA 9401 the data are always processed as unsigned data
D7...D6
FORMAT
D5
FIEINV
D4
VCRMODE
D3
PIMODE NAPIPPH (LSBs of NAPLIP) TWOIN
D2...D1
D0
Subaddress 01 Bit D7...D2 D1 Name VINDEL VINPOL Function VIN input delay: Delay(VIN to internal V-sync) = (128 * VINDEL + 1)*Tclk1 [VINDEL = 0] VIN polarity: 1: low active 0: high active HIN polarity: 1: low active 0: high active
D0
HINPOL
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Preliminary Data Sheet
SDA 9401
Subaddress 02 Bit D7...D2 D1 Name NALIP PLL1OFF Function Number of not active lines per field in the input data stream: Not active lines = NALIP+3 [NALIP= 20] PLL1 switch: 1: off 0: on Internal refresh: 1: on 0: off
D0
REFRESH
Subaddress 03 Bit D7...D0 Name ALPFIP Function Number of active lines per field in the input data stream: Active lines = ALPFIP * 2 [ALPFIP=144]
Subaddress 04 Bit D7...D0 Name NAPIPDL (MSBs of NAPLIP) Function Number of not active pixels from HIN to the input data in system clocks of CLK1: Number(HIN to input data) = (4 * NAPIPDL + NAPIPPH + 8) [NAPIPDL= 0]
Subaddress 05 Bit Name Function Number of active pixels per line in the input data stream in system clocks of CLK1: Active pixels = APPLIP*32 [APPLIP = 45] Inside the SDA 9401 the number of active pixels per line is APPL*32, with APPL = APPLIP, MULITPIC = 0 and HDECON = 0 (APPLIP + 1)/2, MULTIPIC = 0 and HDECON = 1 (APPLIP + 3)/4, MULTIPIC = 0 and HDECON = 2 45, MULTIPIC > 0 x
D7...D2
APPLIP
D1...D0
x
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Preliminary Data Sheet
SDA 9401
Subaddress 06 Bit D7...D0 Name OPDEL Function Output processing delay (in number of lines): Delay(VIN to VOUT) = (OPDEL + 1) * Tline [OPDEL = 170]
Subaddress 07 Bit D7...D0 Name VERWIDTH Function Vertical width of inserted picture in input lines: Vertical width = (2 * VERWIDTH) [VERWIDTH = 0]
Subaddress 08 Bit D7...D0 Name VERPOS Function Vertical position of inserted picture in input lines: Vertical position = (2 * VERPOS) + NALIP + 3 [VERPOS = 0]
Subaddress 09 Bit D7...D2 D1...D0 Name HORWIDTH PLL1RA(1...0) Function Horizontal width of inserted picture in system clocks of CLK1: Horizontal width = (32 * HORWIDTH) [HORWIDTH = 0] PLL1 range, only for test purposes [PPL1RA=0]
Subaddress 0A Bit D7...D2 D1...D0 Name HORPOS PLL1RA(3...2) Function Horizontal position of inserted picture in system clocks of CLK1: Horizontal position = (32 * HORPOS) + (4 * NAPIPDL + NAPIPPH + 8) [HORPOS = 0] PLL1 range, only for test purposes [PPL1RA=0]
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Preliminary Data Sheet
SDA 9401
Subaddress 0B Bit D7...D0 Name NALOP Function Number of not active lines per frame in the output data stream: Not active lines = 2 * (NALOP + 1) [NALOP= 22]
Subaddress 0C Bit D7...D0 Name ALPFOP Function Number of active lines per output frame: Active lines = 4 * ALPFOP [ALPFOP= 144]
Subaddress 0D Bit D7...D0 Name LPFOP Function Number of lines per output frame (only valid for VOUTFR=1): Number of lines = 4 * LPFOP + 1 [LPFOP = 156]
Subaddress 0E Bit D7...D0 Name NAPOP Function Number of not active pixels (coloured border values) from external HREF to the first active pixel of the output data stream in system clocks of X1/ CLK2: Distance(HREF to output data) = (4 * NAPOP) [NAPOP = 0]
Subaddress 0F Bit D7...D0 Name HOUTDEL Function HOUT delay: Delay(HOUT to HREF) = (4 * (HOUTDEL + 1) + 36) *Tx1/clk2 [HOUTDEL = 4]
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Preliminary Data Sheet
SDA 9401
Subaddress 10 Bit D7...D2 Name APPLOP Function Number of active pixels per line (including coloured border values and data) in the output data stream in system clocks of X1/CLK2 (length of HREF): Active pixels = 16 * APPLOP [APPLOP = 45] Reduces the active pixels per line (APPL) at the output side: Active pixels per line at the output side in system clocks of X1/CLK2 = 16 * APPL - 2 * k k= 24: CAPP = 11 16: CAPP = 10 8: CAPP = 01 0: CAPP = 00
D1...D0
CAPP
Subaddress 11 Bit D7...D0 Name PPLOP(7...0) Function Number of pixels between two output H-syncs HOUT (only valid for HOUTFR=1) in system clocks of X1/CLK2 (Bit 7 to 0): Number of pixels = 2 * PPLOP [PPLOP = 432]
Subaddress 12 Bit D7 Name PPLOP(8) Function Number of pixels between two output H-syncs HOUT (only valid for HOUTFR=1) in system clocks of X1/CLK2 (Bit 8): Number of pixels = 2 * PPLOP [PPLOP = 432] Static operation modes (see also Operation 34): 0010: AABB mode I interlaced should be set to 000
mode generator on page
D6...D3 D2...D0
STOPMODE
Subaddress 13 Bit D7...D6 Name INTMODE(3...2) Function Free programmable INTERLACED signal for AC coupled deflection stages (Bit 3 and Bit 2) [INTMODE3...2 = 0]
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Preliminary Data Sheet
SDA 9401
Subaddress 13 Bit Name Function Vertical expansion factor (see also High on page 41): 63: no vertical expansion : 47: vertical expansion with factor 1.5 : 31: vertical expansion with factor 2 :
data rate processing (HDR)
D5...D0
VERINT
Subaddress 14 Bit D7...D6 D5 D4 RMODE Name INTMODE(1...0) Function Free programmable INTERLACED signal for AC coupled deflection stages (Bit 1 and Bit 0) [INTMODE1...0 = 0] should be set to 0 Raster mode: 1: progressive 0: interlaced VOUT generator: 1: freerunning mode 0: locked mode HOUT generator 1: freerunning mode 0: locked mode VOUT (EXSYN=0), VEXT (EXSYN=1) polarity: 1: low active 0: high active HOUT (EXSYN=0), HEXT (EXSYN=1) polarity: 1: low active 0: high active
D3
VOUTFR
D2
HOUTFR
D1
VOUTPOL
D0
HOUTPOL
Subaddress 15 Bit D7 D6 Name WINDVON WINDVDR Vertical window: 1: on 0: off 1: close the vertical window 0: open the vertical window Function
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Preliminary Data Sheet
SDA 9401
Subaddress 15 Bit D5 Name WINDVST Function Status of vertical window after entering vertical window mode: 1: window is opened 0: window is closed Speed of vertical window (see also Window 11: very fast 10: fast 01: medium 00: slow should be set to 000
generator on page 37):
D4...D3
WINDVSP
D2...D0
Subaddress 16 Bit D7 D6 D5 Name WINDHON WINDHDR WINDHST Horizontal window: 1: on 0: off 1: close the horizontal window 0: open the horizontal window Status of horizontal window after entering horizontal window mode: 1: window is opened 0: window is closed Speed of horizontal window (see also Window generator on page 37): 11: very fast 10: fast 01: medium 00: slow Output of system clock CLKOUT: 1: enabled 0: disabled PLL2 switch: 1: off 0: on x Function
D4...D3
WINDHSP
D2
CLKOUTON
D1 D0
PLL2OFF x
Subaddress 17 Bit D7...D4 Name YBORDER Function Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0 0 0 = 00010000 = 16), YBORDER defines the 4 MSB's of a 8 bit value
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Preliminary Data Sheet
SDA 9401
Subaddress 17 Bit D3 Name FLASHON Flash of output picture: 1: on 0: off Chrominance output format: 1: 2's complement input (-128...127) 0: unsigned input (0...255) inside the SDA 9401 the data are always processed as unsigned data should be set to 00 Function
D2 D1...D0
TWOOUT
Subaddress 18 Bit D7...D4 D3...D0 Name UBORDER VBORDER Function U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0 0 0 = 10000000 = 128), UBORDER defines the 4 MSB's of a 8 bit value V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0 0 0 = 10000000 = 128), VBORDER defines the 4 MSB's of a 8 bit value
Subaddress 19 Bit D7...D4 D3 Name PLL2RA CLK21EN Function PLL2 range, only for test purposes [PPL2RA=0] PLL2 input signal (see also Clock concept on page 27): 1: external CLK1 0: external X1/CLK2 Internal clock switch for CLKOUT (see also Clock 1: PLL2 output 0: external CLK1 should be set to 00
concept on page 27):
D2 D1...D0
CLK11EN
Subaddress 1A Bit D7...D0 Name VPAN Function Vertical adjustment of the output picture [VPAN = 0]
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Preliminary Data Sheet
SDA 9401
Subaddress 1B Bit Name Function Multipicture modes: 11: sixteenfold 10: twelvefold 01: fourfold 00: off (In case of MULTIPIC>0, spatial and temporal noise reduction as well as the motion detection for scan rate conversion are disabled) Position for the picture in the multipicture mode (only valid for MULTIPIC > 0, see also Multipicture display on page 18) [PICPOS = 0] Freeze mode (frozen picture): 1: on 0: off should be set to 0
D7...D6
MULTIPIC
D5...D2 D1 D0
PICPOS FREEZE
Subaddress 1C Bit Name Function Vertical decimation of the input data stream: 111: not used 110: factor 4.0 101: factor 3.0 100: factor 2.0 011: factor 1.75 010: factor 1.5 001: factor 1.25 000: off (In case of VDECON>0, spatial noise reduction as well as the motion detection for scan rate conversion are disabled) Horizontal decimation of the input data stream: 11: not used 10: factor 4.0 01: factor 2.0 00: off (In case of HDECON>0, spatial noise reduction as well as the motion detection for scan rate conversion are disabled) should be set to 001
D7...D5
VDECON
D4...D3
HDECON
D2...D0
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Preliminary Data Sheet
SDA 9401
Subaddress 1D Bit D7 Name NRON Function Temporal noise reduction of luminance and chrominance: 1: enabled 0: disabled Spatial noise reduction of luminance: 1: enabled 0: disabled Vertical spatial noise reduction of chrominance: 1: enabled 0: disabled Horizontal spatial noise reduction of chrominance: 1: enabled 0: disabled should be set to 00 TNRSEL Motion detection of temporal noise reduction of chrominance: 1: separate motion detector 0: luminance motion detector Noise measurement algorithm: 1: measurement during vertical blanking period (line can be defined by NMLINE) 0: measurement in the active picture (first active line)
D6
SNRON
D5
VCSNRON
D4 D3...D2 D1
HCSNRON
D0
NMALG
Subaddress 1E Bit D7...D4 Name TNRCLY Function Temporal noise reduction of luminance: classification 1111: slight noise reduction : 0000: strong noise reduction Temporal noise reduction of chrominance: classification 1111: slight noise reduction : 0000: strong noise reduction
D3...D0
TNRCLC
Subaddress 1F Bit D7...D4 Name TNRKOY Function Temporal noise reduction of luminance: Vertical shift of the motion detector characteristic [TNRKOY=0]
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Preliminary Data Sheet
SDA 9401
Subaddress 1F Bit D3...D0 Name TNRKOC Function Temporal noise reduction of chrominance: Vertical shift of the motion detector characteristic [TNRKOC=0]
Subaddress 20 Bit D7...D4 D3...D0 Name TNRVAY TNRVAC Function Fixed K-factor for temporal noise reduction of luminance [TNRVAY = 15] Fixed K-factor for temporal noise reduction of chrominance [TNRVAC = 15]
Subaddress 21 Bit D7...D2 D1 D0 Name TNRHOY TNRFIY Function Temporal noise reduction of luminance: Horizontal shift of the motion detector characteristic [TNRHOY=0] Fixed K-factor switch for temporal noise reduction of luminance: 1: off 0: on should be set to 0
Subaddress 22 Bit D7...D2 D1 D0 Name TNRHOC TNRFIC Function Temporal noise reduction of chrominance: Horizontal shift of the motion detector characteristic [TNRHOC=0] Fixed K-factor switch for temporal noise reduction of chrominance: 1: off 0: on should be set to 0
Subaddress 28 Bit D7...D3 Name NMLINE Function Line for noise measurement (only valid for NMALG=1) [NMLINE = 4]
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Preliminary Data Sheet
SDA 9401
Subaddress 28 Bit D2...D1 D0 x Name should be set to 01 x Function
Subaddress 32 Bit D7...D3 Name NOISEME Function Noise level of the input signal: 0 (no noise), ..., 30 (strong noise) [31 (strong noise or measurement failed )] Version of SDA 94XX family: 000: SDA 9400 001: SDA 9401 010: SDA 9402
D2...D0
VERSION
Subaddress 33 Bit D7...D5 D4 Name xxx TVMODE xxx TV mode of the input signal 1: NTSC 0: PAL Status bit for subaddresses, which will be made valid by VIN 1: New write or read cycle can start 0: No new write or read cycle can start Status bit for subaddresses, which will be made valid by OPSTART 1: New write or read cycle can start 0: No new write or read cycle can start x Status bit for noise measurement parameter: 1: New value of NOISEME available 0: No new value of NOISEME available Function
D3
VISTATUS
D2 D1 D0
OSSTATUS x NMSTATUS
Subaddress FF Bit D7...D0 Name Function Store command for all subaddresses
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Preliminary Data Sheet
SDA 9401
7
Absolute maximum ratings
Parameter
Operating Temperature Storage Temperature Junction Temperature Soldering Temperature Soldering Time Input Voltage Output Voltage Input Voltage Output Voltage Supply Voltages Total Power Dissipation ESD Protection
Symbol
TA
Min
0 -65
Max
70 125 125 260 10
Unit
C C C C s V V V V V W kV
Remark
-0.3 -0.3 -0.3 -0.3 VDD -0.3 -2,0
VDD+0.3 VDD+0.3 5.5 5.5 3.8 1 2,0
not valid for IC bus pins not valid for IC bus pins IC bus pins only IC bus pins only
MIL STD 883C method 3015.6, 100pF, 1500 (HBM) EOS/ESD Assn. Standard DS 5.3-1993 (CDM) all inputs/outputs
ESD Protection Latch-Up Protection
-1,5 -100
1,5 100
kV mA
All voltages listed are referenced to ground (0V, VSS) except where noted. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
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Preliminary Data Sheet
SDA 9401
8
Recommended operating conditions
Parameter
Supply Voltages Ambient Temperature
Symbol
VDD TA VIH VIL IIN VOH VOL VOL
Min
3.15 0 2.0 -0.2
Nom
3.3 25
Max
3.45 70 VDD +0.2 0.8 +/- 5
Unit
V C V V A V
Remark
All TTL Inputs
High-Level Input Voltage Low-Level Input Voltage Input Current
All TTL Outputs
High-Level Output Voltage Low-Level Output Voltage 2.4 0.4 0.5 27 10 10 10 10 22 22 10 10 27 10 10 5 5 3 0 0 1.3 0.6 5.25 1.5 400 IOH = -2.0 mA IOL = 2.0 mA at IOL = max see diagr. 11.3 V V MHz ns ns ns ns ns ns ns ns MHz ns ns ns ns V V kHz s s see diagr. 11.1 see diagr. 11.2 see diagr. 11.3 see diagr. 11.3
INPUT/OUTPUT: SDA
Low-Level Output Voltage
Clock TTL Input CLK1
Clock frequency Low time High time Rise time Fall time
1/T
tWL tWH tTLH tTHL tWL2 tWH2 tTLH2 tTHL2
Input SYNCEN
Low time High time Rise time Fall time
Clock TTL Input X1/CLK2
Clock frequency Low time High time Rise time Fall time High-Level Input Voltage Low-Level Input Voltage SCL Clock Frequency Inactive Time Before Start Of Transmission Set-Up Time Start Condition
1/T
tWL tWH tTLH tTHL VIH VIL fSCL tBUF tSU;STA
IC bus (All Values Are Referred To min(VIH) And max(VIL)), fSCL = 400 KHz
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Preliminary Data Sheet
SDA 9401
Parameter
Hold Time Start Condition SCL Low Time SCL High Time Set-Up Time DATA Hold Time DATA SDA/SCL Rise Times SDA/SCL Fall Times Set-Up Time Stop Condition Output valid from clock Input filter spike suppression (SDA and SCL pins) Low-Level Output Current Crystal frequency Equivalent parallel Capacitance Equivalent parallel Capacitance
Symbol
tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tR tF tSU;STO tAA tSP IQL xtal Cin Cout
Min
0.6 1.3 0.6 100 0
Nom
Max
Unit
s s s ns s
Remark
300 300 0.6 900 50 3 27.0 27 27
ns ns s ns ns mA see diagr. 11.4 MHz pF pF fundamental crystal
Inputs crystal connections X1/CLK2, X2
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Preliminary Data Sheet
SDA 9401
9
Characteristics (Assuming Recommended Operating Conditions)
Parameter
Average Supply Current
Symbol
Min
t.b.d.
Max
t.b.d. 10
Unit
mA pF A ns ns ns
Remark
All VDD pins, typ. t.b.d. mA
All Digital Inputs (Including I/O Inputs)
Input Capacitance Input Leakage Current Set-Up Time Input Hold Time Hold time Delay time Hold time Delay time Set-Up Time Input Hold Time tSU tIH tOH tOD tOH tOD tSU tIH 25 0 6 25 -5 7 6 6 25 5
TTL Inputs: YIN, UVIN, HIN, VIN (Referenced To CLK1)
see diagr. 11.3
TTL Outputs: YOUT, UVOUT, HREF, INTERLACED (Referenced To CLKOUT*)
see diagr. 11.3 CL = 30 pF, 27 MHz see diagr. 11.3 CL = 50 pF, 27 MHz see diagr. 11.3 ns ns ns ns ns
TTL Outputs: HOUT, VOUT (Referenced To CLKOUT)
TTL Inputs: SYNCEN (Referenced To CLK1)
*: see also Clock concept on page 27
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Preliminary Data Sheet
SDA 9401
10 Application information
R G CVBS Y/C RGB VPC32xxD Color Decoder SDA 9401
SCARABAEUS
DDP3310B Deflection controller
B
E/W V-Drive H-Drive
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Preliminary Data Sheet
SDA 9401
11 Waveforms
11.1 IC-bus timing START/STOP
11.2
IC-bus timing DATA
tf t HIGH t LOW tR
BUS TIMING DATA
SCL t SU;STA SDA IN t SP tAA SDA OUT tAA tHD;STA t HD;STA t SU;DAT
t SU;STO
i2ctimdat
t BUF
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Preliminary Data Sheet
i2ctimd01
SDA 9401 11.3 Timing diagram clock T CLK1 CLKOUT tWH tHL tWL VIH VIL tSU2 SYNCEN tWH2 tIH2
Datain Datain
tLH tWL2
tHL2
tLH2
tIH
Dataout
tOD
tSU
Dataout
tOH
11.4
Clock circuitry diagram X1/CLK2 X2
xtal
quartz
Cin
Cout
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Preliminary Data Sheet
SDA 9401
12 Package Outlines
P-MQFP-64
[All dimensions in mm]
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Preliminary Data Sheet
SDA 9401
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-558-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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